TMOD=Val_0x0, SCPH=Val_0x0, SSTE=Val_0x0, SCPOL=Val_0x0, SPI_HYPERBUS_EN=Val_0x0, FRF=Val_0x0, SPI_FRF=Val_0x0, SRL=Val_0x0
OSPI Control Register 0
| DFS | Data Frame Size. Selects the data frame length. When the data frame size is programmed to be less than 32-bits, the receive data is automatically right-justified by the receive logic, with the upper bits of the receive FIFO zero-padded. Software must right-justify transmit data before writing into the transmit FIFO. The transmit logic ignores the upper unused bits when transmitting the data. Note: The DFS value must be, multiple of 2 if SPI_FRF = 0x1, multiple of 4 if SPI_FRF = 0x2, and multiple of 8 if SPI_FRF = 0x3. 3 (Val_0x3): 04-bit serial data transfer 4 (Val_0x4): 05-bit serial data transfer 5 (Val_0x5): 06-bit serial data transfer 6 (Val_0x6): 07-bit serial data transfer 7 (Val_0x7): 08-bit serial data transfer 8 (Val_0x8): 09-bit serial data transfer 9 (Val_0x9): 10-bit serial data transfer 10 (Val_0xA): 11-bit serial data transfer 11 (Val_0xB): 12-bit serial data transfer 12 (Val_0xC): 13-bit serial data transfer 13 (Val_0xD): 14-bit serial data transfer 14 (Val_0xE): 15-bit serial data transfer 15 (Val_0xF): 16-bit serial data transfer 16 (Val_0x10): 17-bit serial data transfer 17 (Val_0x11): 18-bit serial data transfer 18 (Val_0x12): 19-bit serial data transfer 19 (Val_0x13): 20-bit serial data transfer 20 (Val_0x14): 21-bit serial data transfer 21 (Val_0x15): 22-bit serial data transfer 22 (Val_0x16): 23-bit serial data transfer 23 (Val_0x17): 24-bit serial data transfer 24 (Val_0x18): 25-bit serial data transfer 25 (Val_0x19): 26-bit serial data transfer 26 (Val_0x1A): 27-bit serial data transfer 27 (Val_0x1B): 28-bit serial data transfer 28 (Val_0x1C): 29-bit serial data transfer 29 (Val_0x1D): 30-bit serial data transfer 30 (Val_0x1E): 31-bit serial data transfer 31 (Val_0x1F): 32-bit serial data transfer |
| FRF | Frame Format. Selects which serial protocol transfers the data. 0 (Val_0x0): Motorola SPI Frame Format |
| SCPH | Serial Clock Phase. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0, data are captured on the first edge of the serial clock. When SCPH = 1, the serial clock starts toggling one cycle after the slave select line is activated, and data are captured on the second edge of the serial clock. 0 (Val_0x0): Serial clock toggles in middle of first bit. 1 (Val_0x1): Serial clock toggles at start of first bit. |
| SCPOL | Serial Clock Polarity. Used to select the polarity of the inactive serial clock, which is held inactive when the OSPI master is not actively transferring data on the serial bus. 0 (Val_0x0): Inactive state of serial clock is low. 1 (Val_0x1): Inactive state of serial clock is high. |
| TMOD | Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In Transmit Only mode, data received from the external device is not valid and is not stored in the receive FIFO memory; it is overwritten on the next transfer. In Receive Only mode, transmitted data are not valid. After the first write to the transmit FIFO, the same word is retransmitted for the duration of the transfer. In transmit-and-receive mode, both transmit and receive data are valid. The transfer continues until the transmit FIFO is empty. Data received from the external device are stored into the receive FIFO memory, where it can be accessed by the host processor. 0 (Val_0x0): Transmit and Receive; Not Applicable in enhanced SPI operating mode. 1 (Val_0x1): Transmit Only mode; Or Write in enhanced SPI operating mode. 2 (Val_0x2): Receive Only mode; Or Read in enhanced SPI operating mode. 3 (Val_0x3): EEPROM Read mode; Not Applicable in enhanced SPI operating mode. |
| SRL | Shift Register Loop. Used for testing purposes only. When internally active, connects the transmit shift register output to the receive shift register input. 0 (Val_0x0): Normal mode operation 1 (Val_0x1): Test mode operation |
| SSTE | Slave Select Toggle Enable. While operating in SPI mode with SCPH set to 0, this bit controls the behavior of the slave select line between data frames. 0 (Val_0x0): The slave select line will stay low and OSPI_SCLK will run continuously for the duration of the transfer. 1 (Val_0x1): The slave select line will toggle between consecutive data frames, with the serial clock (OSPI_SCLK) being held to its default value while the slave select line is high. |
| SPI_FRF | SPI Frame Format Selects data frame format for Transmitting/Receiving the data. 0 (Val_0x0): Standard SPI format 1 (Val_0x1): Dual SPI format 2 (Val_0x2): Quad SPI format 3 (Val_0x3): Octal SPI format |
| SPI_HYPERBUS_EN | SPI HyperBus Frame Format Enable. Selects if data frame format for Transmitting/Receiving data is in HyperBus mode. 0 (Val_0x0): Disable HyperBus format. 1 (Val_0x1): Enable HyperBus format. |